FUNCTIONAL DESCRIPTION

• Two 16-bit digital I/O module sites, one SMB connector for external clock/synchronization
• One Altera FLEX10K30 programmed as a 32/64-bit PCI controller (3V)
• One 80MHz SHARC 21160 for control and signal processing
• One Altera FLEX10K100E PLD for software programmable front-end bit processing
• Two GC4016 Digital Receivers for up to 8 channels of tune/filter/decimate processing

All components are software configurable to support a variety of processing needs including:

• high speed data acquisition/playback of serial and/or parallel digital data
• an attached DSP processor (FFT processing power ~= 1 Alpha CPU at 233 MHz)
• digital tuning
• FM demodulation
• T1 or E1 multiplexing/demultiplexing interfaces
• time-code processor

The IOC code is user downloadable.  See the IOC bullet for available algorithms.