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Innovative Computer Engineering

The 16-bit digital I/O module sites will accept a TTL ribbon cable connector or one of the 2x2.6in form factor modules listed below. The module sites use Altera PLDs to perform optional clock and MSB inversion, muxing/demuxing of data bits, and stripping off time code bits to be processed by the DSP controllers. The standard FPGA program supports 1,4,8, or 16 bit data words. If an ICE-A2D or ICE-D2E is connected, the FPGA is also used generate a sampling clock if not supplied externally. Dual module sites are clocked independently to allow for short/long term clock skew or different sampling rates. They may also be locked to either one of the sources. For mechanical reasons, the ECL output modules use the external sync/clock signal from the motherboard or an internally generated clock.

If you need to remove an I/O module on a ICE-PIC card please click here for instructions. For specific measurements for PIC5XL I/O modules please click here.


DIGITAL MODULES

 

ICE-DR2D Differential Receiver Input Module ($250 In Production)

ICE-E2D  Differential ECL Input Module  ($250 In production)

ICE-D2E  Differential ECL Output Module  ($250 In production) *ICE-PE2D*  Differential PECL Input Module  ($250 In production)  ICE-T2D  Differential TTL Input Module  ($250 In production)

*ICE-D2T*   Differential TTL Output Module ($250 In production)

*ICE-LV2D* LVDS Input Module  ($250 In production) 

*ICE-D2LV* LVDS Output Module  ($250 In production) 

*ICE-GigEXD-r2* ($3000 - $3100 In Production)