Help: ICE_FLAGS
Flags are typically specified in the config string with either a comma ","
or vertical bar "|" as a seperator. They modify the standard behavior of
the library routines as noted. The ICE Midas primitives take a FLAGS switch
to add flags to the current config string. For instance:
SOURCEPIC/flags=(VHS|MUXCLK=A|MSBI)
NOTE: The flags argument in the ioport() routine are NOT for tuner flags.
The tuner flags must be placed in the config string.
Clocking:
MUXCLK=S - IOC code allowing choice of 6 on-board clock sources
INTCLK - Internally generate clock for IO modules (same as MUXCLK=I)
CLKI - Invert input clock
CLKRE - Latch data on Rising Edge of Clock instead of default falling edge
NCCLK - Normally, the 1st clock cycle is used to synchronize the enabling of a
PREFX - This option uses the eXternal pin as a reference for the Programmable Clock
CCLK=F - Specifies the non-standard value of the CCLK crystal in Hertz.
DEGLITCH - Enables deglitch circuit for MUXCLK inputs
CLKDLY=N - Delays input clock by N nanoseconds for clock/data deskew
PRETRIG=N - Capture N cycles before trigger
PMTHROTTLE=N - throttles Processor Module output to n Mby/s
Data Routing:
MSBI - Invert the Most Significant Bit
LSBX - Replace the LSB with the data on the eXternal sync pin
BIT=N - Which bit for single bit acquisitions (0,1,4, or default=15 the MSB)
MBITS=N - When using a Tuner or Core port, this can be used to specify a non-default data
ALT - Use alternate numbered port as source of data
INP=N - Use input n=1 or input n=2 to feed the port
IPORT=PORT - This specifies a non-default input routing for a CORE or TUNER port
OPORT=PORT - This specifies a non-default output routing for a CORE or TUNER port
DELAYPORT=PORT - Select which ports 1=oddTuners 2=evenTuners or 3=allTuners (fed by port1) to
Triggering:
SGO - Slave acq/playback start to opposite channel acting as master
RGO - Ready acq/playback to start with channel on the same side.
TGO - Use bit0 (or ext SMB if XGO and TGO) to trigger start
GGO - Use bit1 (or ext SMB if XGO and GGO) to gate the input clock
XGO - Applied with TGO, GGO, or SGO to use external sync SMB
XTGO - Shorthand for applying XGO and TGO.
XSTGO - Shorthand for applying XGO, SGO and TGO.
XSOE - Enable external sync SMB output
TPOE=N - Enable Test Port output on 5 series cards
XSTP - Use the internal test port on the PIC5 to implement the XGO trigger
Tuners:
CHNS=N - Specify the number of configured tuner channels.
CPC=N - Specify the number of channels per tuner chip
CFIR=NAME - Load the named file into the tuner Coarse (post CIC) Filter.
RFIR=NAME - Load the named file into the tuner resampler Filter
PFIR=NAME - Load the named file into the tuner Programmable (post CFIR) Filter.
FFIR=NAME - Load the named file into the special Filter Only Core
FIRONLY - Bypasses the front end of the FPGA based tuners (PIC5+)
UFILT - Use the user defined programmable (PFIR) filter in tuner chips
UCFIR - Use the user defined coarse (CFIR) filter in tuner chips
URFIR - Use the user defined resampler (RFIR) filter in tuner chips on PIC5 boards
NCFIR - Use the narrow-band CFIR coefficients on Graychips.
PFIR4 - Decimate by 4 instead of 2 in PFIR stage on Graychips.
OVSR=N - Set the tuner oversampling factor to N
AOVSR - Automatically apply oversampling ratio to allow lower tuner decimation.
POVSR - Use Post OVSR input rate as the basis for decimation and frequency parameters.
DSYNC - Turn off tuner NCO dither function
FSYNC - Synchronize tuner frequency changes
TALT1 - All tuners on INP=1 to make a SLIC3 act like half of a PIC4T
ITDEC - Allow independent tuner decimation for each channel on a GC4016.
ITFMT - Allow independent tuner format (SI|CI) for each channel on a GC4016 chip
ITCPC - Allow independent tuner Channels Per Chip (CPC=1|2|4) for each chip on a DTDM or DTDMX.
RESAMP - Enables digital resampling in the tuner
PRESAMP - Enables digital resampling in a tuner core placed in front of this resource
NORESMON - Disable the PIC5 tuner resampler M over N circuit in favor of a straight
TCLK=N - Sets the internal clock frequency for the Graychips on DTDM/DTDMX modules
FTTM=N - Fast Tuner Transform Mode controls various bank of tuners algorithms.
High Speed:
HS - Use HighSpeed DMA link port mode (automatic for module/tuner ports).
DUAL - Use two link ports per module (automatic when xfer rate > 38Mby/sec).
VHS - Use SHARC link ports in 48 bit mode for maximum transfer rates.
MEM=ALL - Specify card circular buffer memory to use ALL available
MEM=EXT - Specify card circular buffer memory to use extended memory
CSIZE=N - Specify card circular buffer memory in 1K byte blocks.
COFFS=N - Specify card circular buffer memory offset in 1K byte blocks.
FRAMEDELAY - Delays output of frame decimated output by one frame
Debug:
VERBOSE - Print commands/status to screen (for debugging)
NOLOCK - Bypass multi-user locking mechanism (for debugging)
PKTHDR - Continuously capture last ICE/SDDS Header in buffer for use by the PKTHDR key function.
TO=N - Timeout value in seconds for DMA_WAIT function
TP=N - Test Port number
B32 - Only use lower 32 bits of PCI bus (ES45 hot-swap PCI workaround)
FORCE - Force reload of all programmable devices
MODDEBUG=N - Puts IO Module in Debug mode
Config:
NODE=ADDRESS - Specifies the node name this device is plugged in to
IOM=IOMT_NAME - Specifies the type of IO modules on this card by name
IOC=SIG - Specify name of IO Controller file to load during a reset
SOC=SIG - Specify name of SystemOnChip file to load into 5 series FPGA
PM=PMT_NAME - Specifies the type of Processor modules on this card by name
NOPM - Specify that there are no Processor Modules on this PIC4X or PIC5X card
AUTOCONFIG - Performs autoconfig of IO and Processing modules during reset
PRC=SIG - Specify name of PRoCessor load file to use, default is "def"
PPC=SIG - Specify name of PowerPC load file to use on a Processor Module, default is "def"
IOMWAIT=SEC - Number of seconds to wait after module reload for configuration discovery.
Network:
IPVLAN=VLAN - Specify the Default Virtual Local Area Network address for this UDP module
IPADDR=IP - Specify the IP address of this UDP module
IPCONN=IP - Specify the IP address of for the UDP module to connect to
IPDISC=IP - Specify the IP address of for the UDP module to disconnect from
IPDEST=IP - Specify the IP address of for the UDP module to send to
Network Debug:
RXICESDDS - The default SDDS mode (Native Mode) for proper tuner|module operation and timecode interpretation.
RXRAWDATA - Bring In Every And All Packets Data/Headers.
RXRAWBURST - Bring In All Packet wout/Tx Response.
RXRAWSDDS - Bring In Only SDDS Packet Header & Data, NO UDP,IP Hdrs.
RXSDDSDATA - Bring In Only SDDS Data, No Headers
RXPKTSDDS - Bring In Data With ICE (8 Byte) & SDDS Headers And SDDS Data Without Need For IIS or IOS Download
RXALLOWPRYPKT - Allow Acquisition Of SDDS Parity Pkts.
RXALLOWNSPKT - Allow Acquisition Of Non-Standard SDDS Pkts.
RXSTRICTOFF - Allow Multiple MC Joins.
RXNOSEQFILL - Do NOT insert filler for dropped SDDS packets based on sequence checks.
RXTCBSWAP - Swaps bits 0 and 3 in 16 bit SDDS packets to move TimeCodeBit=3 into selectable bit=0.
TXRAWDATA - Send Out Packets With 1080 Bytes Of Data, All From User, SDDS Hdr Not Generated
TXRAWSDDS - Send Out Packets With SDDS Hdr (56 Bytes) Generated By Module, 1024 Bytes From User
TXVLANOVRIDE - Enable protected VLAN range used to insert a signal into the SDDS network
SDDSLEAK=N - Leaks the SDDS packet data at the nominal rate to prevent tuner starvation at low
NOLINK - Disable link negotiation.
TimeCode:
TC=MODE - Set the timecode mode as described in the help on pic_tc.
OKNC - Turn off clock loss detect circuit.
NOTCFILL - Do Not require fill bits prior to barker in SDN and DTL modes
OPPSOFFSET=N - Number of clock cycles offset between the 1PPS signal capture and the data capture.
ATCCALIB=N - Additional timecode calibration in units of post tuner/core samples