ICE-CHIPS
Specs for DSP chips used on ICE cards
PCI Controller
The Altera FLEX10K20/30 is programmed
as a 32/64 bit PCI master/target controller responsible for handling communication
between the host and the SHARC. Mailboxes in this chip are used to
send command packets from the host and present a response from the SHARC.
The SHARC also schedules DMA read or write bursts of up to 1MWord in length
between host and SHARC memory. All ICE devices show up as Altera
based cards 0x1172, with device number 0x7777. The revision number
in the PCI config space stores the card type.
Transfer rates depend on the system PCI controller and bus loading.
This chip is configured from an EPROM at power-up.
SHARC 21062 Processor
The Analog Devices 21062
SHARC is a high performance 32-bit signal processor for speech, sound,
graphics, and imaging applications.
The system-on-a-chip architecture operating at 40 MHz features:
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32-bit IEEE floating point computations (80MFLOPS)
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256 Kby dual-ported SRAM
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Four serial I/O ports capable of transfering 40Mbits/s each (2 input, 2
output)
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Six bi-directional link ports capable of transfering 40Mby/s each
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Ten simultaneous DMA channels (6 link ports, 2 serial ports, and 2 host/PCI
channels)
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Total DMA throughput of up to 240 Mby/s with transparent memory crossbar
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Specs: 1K CFFT in 460uS, continuous 2K RFFTs at 4 MHz
The DMA channels on link ports 1-6 support circular buffering for acquisition/playback
of continuous data sources/sinks without external FIFOs. Handling
continuous DMAs is the primary function of the SHARC interrupt handler
code or executive. Once DMA bursts are scheduled, the main processor
is fully available to user code.
SHARC 21160 Processor
The Analog Devices 21160
SHARC is a high performance 32-bit signal processor for speech, sound,
graphics, and imaging applications.
The system-on-a-chip architecture operating at 100 MHz features:
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32-bit IEEE floating point computations (400MFLOPS)
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512 Kby dual-ported SRAM
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Four serial I/O ports capable of transfering 100Mbits/s each (2 input,
2 output)
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Six bi-directional link ports capable of transfering 100Mby/s each
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Fourteen simultaneous DMA channels (6 link ports, 4 serial ports, and 4
host/PCI channels)
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Total DMA throughput of up to 700 Mby/s with transparent memory crossbar
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Specs: 1K CFFT in 92uS, continuous 2K RFFTs at 20MHz
The DMA channels on link ports 1-6 support circular buffering for acquisition/playback
of continuous data sources/sinks without external FIFOs. Handling
continuous DMAs is the primary function of the SHARC interrupt handler
code or executive. Once DMA bursts are scheduled, the main processor
is fully available to user code.
SHARC 21161 Processor
The Analog Devices 21161
SHARC is a high performance 32-bit signal processor for speech, sound,
graphics, and imaging applications.
The system-on-a-chip architecture operating at 100 MHz features:
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32-bit IEEE floating point computations (400MFLOPS)
-
128 Kby dual-ported SRAM
-
Four serial I/O ports capable of transfering 100Mbits/s each (2 input,
2 output)
-
Two bi-directional link ports capable of transfering 100Mby/s each
-
Ten simultaneous DMA channels (6 link ports, 4 serial ports, and 4 host/PCI
channels)
-
Total DMA throughput of up to 700 Mby/s with transparent memory crossbar
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Integrated SDRAM controller with 400 Mby/s external memory bandwidth
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Specs: 1K CFFT in 92uS, continuous 2K RFFTs at 20MHz
The DMA channels on link ports 1-2 support circular buffering for acquisition/playback
of continuous data sources/sinks without external FIFOs. Handling
continuous DMAs is the primary function of the SHARC interrupt handler
code or executive. Once DMA bursts are scheduled, the main processor
is fully available to user code.
I/O Controller
The Altera programmable gate
array sits between the I/O Modules and the SHARC processor. It is
typically responsible for muxing/demuxing 1, 4, 8, or 16 bit data into
the 4/8-bit link port and controlling the external I/O Modules. It can
also be used to bridge the A and B ports, upsample tuner input data, process
digital time code bits, or other special purpose functions. The FLEX10K20
(ICE-PIC2) has 1152 logic cells and 12288 ram bits. The FLEX10K50
(ICE-PIC3/ICE-MBT3) has 2880 logic cells and 20480 ram bits. The
FLEX20K100E (ICE-PIC4) has 4160 logic cells and 53248 ram bits.
The IOC is programmed in AHDL. The interface design files are
available by request for developers to create their own special purpose
functions. See the IOC help page
for currently available IOC functions.
GC4014 Digital Tuner
The Graychip/TI GC4014 is a 4 channel
digital tuner featuring:
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Input rates up to 65 MSPS
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Four real input down-convert channels, or two complex input down-convert
channels
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Independent tuning frequencies
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Independent phase and gain controls
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Decimation factors of 16 to 8192 in the real output mode, 32 to 16384 in
complex mode
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0.020 Hz tuning resolution at 65 MSPS
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Five stage CIC provides greater than 100dB far image rejection
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116 dB spur free dynamic range
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User programmable 21 and 63 tap decimate by two filters, independent per
channel
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Nyquist filtering for QPSK or QAM symbol data
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Meets GSM, AMPS, DAMPS, IS95, WBCDMA single channel, and MCNS specifications
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250mW per channel at 50MHz, 3.3 volts
At 2 samples per baud, one GC4014 can process 4 signals at 1.45MSymbols/sec.
The decimation must be a multiple of 2 and can range from16 to 32K.
Decimation must be the same for all channels on the same chip.
GC4016 Digital Tuner
The Graychip/TI GC4016 is a 4 channel
digital tuner / resampler featuring:
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Input rates up to 100 MSPS
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Four real input down-convert channels, or two complex input down-convert
channels
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Independent tuning frequencies
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Independent phase and gain controls
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Independent decimation controls
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Decimation factors of 16 to 8192 in the real output mode, 32 to 16384 in
complex mode
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Zero padding for lower decimation factors
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0.020 Hz tuning resolution at 70 MSPS
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Five stage CIC provides greater than 100dB far image rejection
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116 dB spur free dynamic range
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User programmable 21 and 63 tap decimate by two filters, independent per
channel
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Nyquist filtering for QPSK or QAM symbol data
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Resampler provides in/output rate independence, user programmable filter
(up to 512 taps)
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Meets GSM, AMPS, DAMPS, IS95, WBCDMA single channel, and MCNS specifications
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250mW per channel at 50MHz, 3.3 volts
Channels can be ganged together to create two channels at decimate by 8,
or one channel at decimate by 4. This means that at 2 samples per
baud, one GC4016 can process 4 signals at 1.45MSymbols/sec, 2 signals at
2.9MSymbols/sec, or 1 signal at 5.8MSymbols/sec.
The decimation must be a multiple of 2 and can range from16 to 32K in
four channel mode, 8 to 16K in two channel, or 4 to 8K in single channel
mode.
AD6620 Digital Tuner
The Analog Devices AD6620
is a single channel digital tuner featuring:
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Input rates up to 65 MSPS (32.5MSPS in diversity mode)
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Decimation factors of 1 to 16384
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0.020 Hz tuning resolution at 65 MSPS
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2nd order and 5th order CIC provides better than 110dB out of band rejection
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User programmable, maximum 256 tap FIR filter (max 130M taps per second)
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Minimum decimation of 256 with 256 tap filter, 32 with 32 tap filter, 4
with 4 tap filter, etc...
The AD6620 tuners can be used as an FM demod at up to 65MHz by decimating
by 1 and processing the complex output in the IOC gate array to perform
the phase differencing.
The diversity mode allows two inputs with the same clock to be tuned
to the same frequency by a single chip.
AD6640 Analog to Digital Converter
The Analog Devices AD6640
is a single channel A2D Converter featuring:
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Input rates up to 65 MSPS, minimum sample rate of 5MHz
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Two's complement, 12 bit resolution

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