BLOCK DIAGRAM   

The ICE-PIC card is a programmable digital I/O processor combined with a powerful DSP processor and two (optional) digital tuners. It is software configuarble to support a variety of processing needs including:

• high speed data acquisition/playback of serial and/or parallel digital data
• an attached DSP processor ( FFT processing power ~= 1 Alpha CPU at 233 MHz)
• dual-channel narrow band digital tuning (from external or internal source)
• host control of up to six ICE-NBT or ICE-SHARC cards
• T1 or E1 multiplexing/demultplexing interfaces
• time-code processing

The Analog Devices 21062 SHARC is a high performance 32-bit signal processor for speech, sound, graphics, and imaging applications. The system-on-a-chip architicture operating at 33 MHz features:

• 32-bit IEEE floating point computations (66MFLOPS)
• 256 Kby dual-ported SRAM
• Four serial I/O ports capable of transfering 33 Mbits/s each (2 input, 2 output)
• Six bi-directional link ports capable of transfering 33 Mby/s each
• Ten simultaneous DMA channels (6 link ports, 2 serial ports, and 2 host/PCI channels)
• Total DMA throughput of up to 200 Mby/s
• Crossbar switch memory connections
• Interval timer (for ICE-A2D I/O Module clocking, etc.)

S5933 Processor:

The PCI bus interface is handled by the AMCC S5933 PCI Controller chip. It has a bi-directional 8x32bit FIFO and DMA bus mastering capable of sustaining 100+Mby/s writes to and 90+Mby/s reads from host memory on standard PCs. Circular buffers of only 1Kby (in SHARC memory) are necessary to cover bus latencies at the maximim throughput.

FPGA Processor:

The FPGA is responsible for muxing/demuxing 1, 4, 8, or 16 bit data into the 4-bit link port nibbles and controlling the external I/O Modules. It can also be used to bridge the A and B ports. Link ports 6:7 can be routed via ribbon cable to another board, or to SHARC link ports 0:1 to achieve the full external I/O data rate of 132 Mby/s.

DDC Processor Option:

Two Harris Semiconductors HSP50016 Digital Down Converters are available to perform two-channel digital narrow-band tuning. These DSP chips are controlled via the SHARC's serial interface ports. The 16-bit digital input can come from the external I/O Module port or the FPGA via the SHARC link ports. This allows data that is archived on the host (disk or memory) to be processed by the DDC's.

To process external data with time-code, the FPGA routes the timecode bit through the link port to the SHARC processor which decodes the bits and attaches a timestamp to the DDC output (usually complex short or floating point data) at specified intervals.