RI(ICE)-A2DR6

Features

Operation

Clocking: 

        OCLK-  OCLK comes from a clock source (oscillator) socketed on the ICE PCI card (ex. ICE-PIC4T, ICE-PIC3T, ICE-MBT3, etc.) or from a socketed source on the rack mount chassis (ex. RI(ICE)-RMRF2, RI(ICE)-RMRF4).  Because OCLK  is a TTL level signal and runs from a source not on the A2DR6 module (giving it a longer trace length) it is typically under 100 MHz. 

        PECL Oscillator, External Source- From the diagram above, these signals are high speed PECL signals.  Their speeds can be anywhere within the the range of speeds for the A2DR6 digitizing rate (25 MHz -200 MHz).  These signals are short in length and remain on the module when clocking the A2DR6.

        A2DR6 Clock Selection- The A2DR6 can be clocked from several sources.   From the diagram above, their are 3 clock sources-the signal labeled OCLK, the on-board PECL oscillator or an external source (1/2 Vp-p signal ex. sine wave, square wave, etc.). Selection of the on-board PECL oscillator or the external  source is accomplished via jumper J3.  The output of jumper J3 is then "muxed" with  OCLK.  The resultant signal out of the mux of  OCLK signal and the output of J3 drives the A/D converter.  In the the case where the A2DR6 is used on an ICE PCI card the "muxed" clock output to the A/D converter is chosen by the ICE software and depends on user command line instructions.   When the A2DR6 is used in a rack mount chassis the "muxed" clock output to the A/D converter is chosen via external switch settings on the rack mount unit. 

Data Output

        Data Output, Single 8 Bit Samples or Dual Married 8 Bit Samples-  From the description above, when OCLK is selected as the clocking source for the A2DR6 because of its low signal rates (<100 MHz) data out of the module is always single 8 bit samples at the OCLK rate on data bits Dout[15..8].  When either the PECL oscillator or an external signal are chosen as clocking source for the A2DR6, because of its potentially high signal rate (up to 200 MHz) data out of the module is always dual married 8 bit samples at 1/2 the digitizing clock rate.  When using married 8 bit samples, data bits Dout[15..8] represent sample N and bits Dout[7..0] represent sample N+1 in time.

Jumper Settings For Power/Ground And Clock Connections

* 5V Analog Power Via Board Header: Default Power Setting When Delivered

** 5V Analog Power Via External Power Source: No Shunt Used But The User Should Apply External 5V Power To Pins 1 & 2 Of Jumper J1.

* 3.3V Digital Power Via Voltage Regulator: Default Power Setting When Delivered

** 3.3V Digital Power Via External Power Source: No Shunt Used But User Should Apply External 3.3V Power To Pins 2 & 3 Of Jumper J2

* Default Selection When Delivered.

** User Supplied Oscillator-Oscillator should be a Half Size 8 Pin Dip, 5V With PECL (Single Ended) Output

PECL Oscillators can be purchased from FOX Electronics. The JITO-2 series oscillators cover the frequency ranges of 20 Mhz to 250 Mhz. As an example, the part number JITO-2 BP5DM-200.00 would be a Half Size 8 Pin Dip, 5V oscillator at 200 Mhz with single ended PECL output.

* These settings control high speed PECL differential clocking of the A/D converter and should not be changed. They are listed here for reference only. Data corruption will occur if the settings above for the High Speed Clock Configuration are not used.

* FPGA Programming Via Supplied EPROM: Programming of the FPGA for data manipulation is done via the supplied EPROM.

** User Programmable: Engineers who want to design their own FPGA download and program the FPGA need to 1.) set the jumpers as listed. 2.) Remove the EPROM E1. Software for downloading the FPGA program is included in the free software baseline.

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