ICE Help CARDS

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Summary: Brief description of the ICE-DSP cards and I/O Modules

This file contains a brief text description of the ICE-DSP card architecture. Block diagrams are available in HTML formats only.

Contents

Main Boards

PIC1 - PCI (32 bit, 33MHz, 5V) Tuners (HSP50016 x2)

INTRODUCTION

The ICE-PIC is driven by an Analog Devices 21062 SHARC DSP and interfaced to the PCI bus by an AMCC 5933 PCI Controller Chip. It contains module sites for two 16 bit digital in/outputs, two 33Mbit/s serial IO interfaces and two (optional) Harris HSP50016 Digital Down Converters.

INSTALLATION

This card fits in a standard PCI slot on most computers. The edge connector is mounted on flexible brackets to adjust to different manufacturer's chassis tolerances.

Mounting a module requires approximately 1.0 inches of slot width. This is still a single slot on a DEC-4100, but more than one on most other chassis. The extra slot may be used to feed the module cables out of the chassis. On DEC-4100 chassis, the PCI bay door grill can be snipped allowing the cables to exit the PCI bay without using an extra slot. The multi-slot problem is fixed in the ICE-PIC2 revision.

NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly. There are no keys and
    reversing the polarity will damage the board !!!

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by removing any modules and running the TEST procedures macro.


The SHARC port / flag pin mappings are as follows:

DDC 1	<-> Serial Port 1 Rx/Tx
DDC 2	<-> Serial Port 2 Rx/Tx
I/O Module 1 <-> Link Port 3  &  1
I/O Module 2 <-> Link Port 4  &  2
FLG0 -> DDC Reset S5933 DMA enable
FLG1 -> DDC Qstart and FPGA flag
FLG2 -> IOMOD/DDC 2 CS
FLG3 -> IOMOD/DDC 1 CS
BMS  -> External Reset


PIC2 - PCI (64/32 bit, 33MHz, 5V) Tuners (HSP50016 x2)

INTRODUCTION

The ICE-PIC is driven by an Analog Devices 21062 SHARC DSP and interfaced to the PCI bus by an Altera FLEX10K20 programmable logic device. It contains module sites for two 16 bit digital in/outputs, a FLEX10K20 PLD for front end bit processing, two 40Mbit/s serial IO interfaces and two (optional) Harris HSP50016 Digital Down Converters.

INSTALLATION

This card fits in a standard PCI slot. The edge connector has spacers to adjust to different manufacturer's chassis tolerances.

Mounting a module requires approximately 0.6 inches of slot width. The ribbon cables for the E2D, D2E, and T2D are fed behind the card and out the card's edge connector. This keeps the cables from restricting airflow over the component side of the board.

The edge connector has space for 1 SMB connector to provide an external clock for output modules. If ribbon cables are not used (A2D or GXD modules) the ribbon cable strain relief bracket is used to mount 4 more SMB's on the card edge in the ribbon cable's slot. This provides a single slot solution in most cases.

If one module requires ribbon cables and another requires more than one SMB, an extra slot will be required, or the SMB cables can be run through the ribbon cable slot (but not mounted on the card edge).


NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly. There are no keys and
    reversing the polarity can damage the board !!!

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC X-Midas macro. Special IOC programs are loaded to perform loopback tests for all components except the modules.

MBT2 - PCI (64/32 bit, 33MHz, 5V) Tuners (GC4014 x6)

INTRODUCTION

The ICE-MBT2 is driven by an Analog Devices 21062 SHARC DSP and interfaced to the PCI bus by an Altera FLEX10K20 programmable logic device. It contains module sites for two 16 bit digital in/outputs, a FLEX10K20 PLD for front end bit processing, two 40Mbit/s serial IO interfaces, and up to 6 Graychip GC4014 Digital Tuners.

INSTALLATION

This card fits in a standard PCI slot. The edge connector has spacers to adjust to different manufacturer's chassis tolerances.

Mounting a module requires approximately 0.8 inches of slot width. The ribbon cables for the E2D, D2E, and T2D are fed behind the card and out the card's edge connector. This keeps the cables from restricting airflow over the component side of the board.

The edge connector has space for 1 SMB connector to provide an external clock for output modules. If ribbon cables are not used (A2D or GXD modules) the ribbon cable strain relief bracket is used to mount 4 more SMB's on the card edge in the ribbon cable's slot. This provides a single slot solution in most cases.

If one module requires ribbon cables and another requires more than one SMB, an extra slot will be required, or the SMB cables can be run through the ribbon cable slot (but not mounted on the card edge).


NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly. There are no keys and
    reversing the polarity can damage the board !!!

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC X-Midas macro. Special IOC programs are loaded to perform loopback tests for all components except the modules.

MBT3 - PCI (64/32 bit, 33MHz, 5V) Tuners (GC4014 x6)

INTRODUCTION

The ICE-MBT3 is driven by an Analog Devices 21062 SHARC DSP and interfaced to the PCI bus by an Altera FLEX10K30 programmable logic device. It contains module sites for two 16 bit digital in/outputs, a FLEX10K50 PLD for front end bit processing, and up to 6 Graychip GC4014 Digital Tuners.

INSTALLATION

This card fits in a standard PCI slot. The edge connector has spacers to adjust to different manufacturer's chassis tolerances.

Mounting a module requires approximately 0.6 inches of slot width. All external module connectors are available at the card's edge connector.

The edge connector has 1 SMB connector to provide an external clock for output modules or a signal for synchronizing multiple cards. There are 3 jumpers for configuring the external clock/sync connector:

J1 - close for on board 50 ohm termination, open for high impedance
J2 - close for multi-board signaling (external sync), open for clock 
J3 - close for DC coupled TTL clock, open for AC coupled 1Vpp sinusoid clock

To synchronize acquisition/playback between multiple cards, J2 must be in place (closed) for both the master and slaves. The Master asserts the XSOE flags to drive the line. The J1 terminators should be open. Add J3 for 2.5V 10kohm pull-up/dn and diode protection on the input/output.

One on-board crystal X2 is socketed for an optional user supplied reference clock. This clock can be used for driving A2D or D2E modules at fixed rates or for special IOC code rates. By default, X2 is a 65MHz clock for tuner upsampling or maximum bandwidth A2DR4 clocking.

NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC X-Midas macro. Special IOC programs are loaded to perform loopback tests for all components except the modules.

PIC3T - PCI (64/32 bit, 33MHz, 5V) Tuners (AD6620 x2)

INTRODUCTION

The ICE-PIC3T is driven by an Analog Devices 21062 SHARC DSP and interfaced to the PCI bus by an Altera FLEX10K30 programmable logic device. It contains module sites for two 16 bit digital in/outputs, a FLEX10K50 PLD for front end bit processing, and 2 Analog Devices AD6620 Digital Tuners.

INSTALLATION

This card fits in a standard PCI slot. The edge connector has spacers to adjust to different manufacturer's chassis tolerances.

Mounting a module requires approximately 0.6 inches of slot width. All external module connectors are available at the card's edge connector.

The edge connector has 1 SMB connector to provide an external clock for output modules or a signal for synchronizing multiple cards. There are 3 jumpers for configuring the external clock/sync connector:

J1 - close for on board 50 ohm termination, open for high impedance
J2 - close for multi-board signaling (external sync), open for clock
J3 - close for DC coupled TTL clock, open for AC coupled 1Vpp sinusoid clock

To synchronize acquisition/playback between multiple cards, J2 must be in place (closed) for both the master and slaves. The Master asserts the XSOE flags to drive the line. The J1 terminators should be open. Add J3 for 2.5V 10kohm pull-up/dn and diode protection on the input/output.

One on-board crystal X2 is socketed for an optional user supplied reference clock. This clock can be used for driving A2D or D2E modules at fixed rates or for special IOC code rates. By default, X2 is a 65MHz clock for tuner upsampling or maximum bandwidth A2DR4 clocking.

NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC X-Midas macro. Special IOC programs are loaded to perform loopback tests for all components except the modules.

PIC4T - PCI (64/32 bit, 66/33MHz, 3/5V) Tuners (GC4016 x2)

INTRODUCTION

The ICE-PIC4T is driven by an Analog Devices 21160 SHARC DSP and interfaced to the PCI bus by an Altera FLEX10K30E programmable logic device. It contains module sites for two 16 bit digital in/outputs, a FLEX10K100 PLD for front end bit processing, and 2 GrayChip GC4016 Digital Tuners.

INSTALLATION

This card is a universal PCI card. If fits in either 64/32 bit, 3/5V, or 66/33MHz PCI slots. The edge connector has spacers to adjust to different manufacturer's chassis tolerances.

Mounting a module requires approximately 0.6 inches of slot width. All external module connectors are available at the card's edge connector.

The edge connector has 1 SMB connector to provide an external clock for output modules or a signal for synchronizing multiple cards. There are 3 dip switches for configuring the external clock/sync connector:

J1 - close for on board 50 ohm termination, open for high impedance
J2 - close for multi-board signaling (external sync), open for clock
J3 - close for DC coupled TTL clock, open for AC coupled 1Vpp sinusoid clock

Note: on some early models the dip switches are just jumpers.

To synchronize acquisition/playback between multiple cards, J2 must be in place (closed) for both the master and slaves. The Master asserts the XSOE flags to drive the line. The J1 terminators should be open. Add J3 for 2.5V 10kohm pull-up/dn and diode protection on the input/output.

One on-board crystal X2 is socketed for an optional user supplied reference clock. This clock can be used for driving A2D or D2E modules at fixed rates or for special IOC code rates. By default, X2 is a 100MHz clock for maximum bandwidth A2DR7 clocking.

NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC X-Midas macro. Special IOC programs are loaded to perform loopback tests for all components except the modules.

PIC4X - PCI (64/32 bit, 66/33MHz, 3/5V) PM x1

INTRODUCTION

The ICE-PIC4X is driven by an Analog Devices 21160 SHARC DSP and interfaced to the PCI bus by an Altera FLEX10K30E programmable logic device. It contains module sites for two 16 bit digital in/outputs, a FLEX10K100 PLD for front end bit processing, and one processor module site.

INSTALLATION

This card is a universal PCI card. If fits in either 64/32 bit, 3/5V, or 66/33MHz PCI slots. The edge connector has spacers to adjust to different manufacturer's chassis tolerances.

Mounting a module requires approximately 0.6 inches of slot width. All external module connectors are available at the card's edge connector.

The edge connector has 1 SMB connector to provide an external clock for output modules or a signal for synchronizing multiple cards. There are 3 dip switches for configuring the external clock/sync connector:

J1 - close for on board 50 ohm termination, open for high impedance
J2 - close for multi-board signaling (external sync), open for clock
J3 - close for DC coupled TTL clock, open for AC coupled 1Vpp sinusoid clock

Note: on some early models the dip switches are just jumpers.

To synchronize acquisition/playback between multiple cards, J2 must be in place (closed) for both the master and slaves. The Master asserts the XSOE flags to drive the line. The J1 terminators should be open. Add J3 for 2.5V 10kohm pull-up/dn and diode protection on the input/output.

One on-board crystal X2 is socketed for an optional user supplied reference clock. This clock can be used for driving A2D or D2E modules at fixed rates or for special IOC code rates. By default, X2 is a 100MHz clock for maximum bandwidth A2DR7 clocking.

NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC X-Midas macro. Special IOC programs are loaded to perform loopback tests for all components except the modules.

MBT4 - a PIC4X with a DTDM processor module

Specifying PM1=DTDM in the card config string of a PIC4X causes the software to use tuner resources on the processor module.

This is the default on a PIC4X unless PM1=NONE is specified.

MBT4X - a PIC4X with a DTDMX processor module

Specifying PM1=DTDMX in the card config string of a PIC4X causes the software to use tuner resources on the processor module. The DTDMX must be specified to allow the software to talk to this module, the default is a DTDM module.

PIC5 - PCI (64/32 bit, 133/100/66/33MHz, 3V) PM x2

This card is a 3.3V only PCI card. If fits in either 64/32 bit, 3V, 133/66/33MHz PCI slots. Jumper J4 is closed for PCI, open for PCI-X. Currently, PCI-X mode is not supported.

The card has a status LED next to the edge connector SMB. When the card is booted, the green LED flashes at 1Hz=66MHzPCI, 1.5Hz=100MHzPCI, or 2Hz=133MHz PCI. The red LED indicates PC transfers to/from the card.

Mounting an I/O module requires approximately 0.6 inches of slot width. All external module connectors are available at the card's edge connector.

The edge connector has 1 SMB connector to provide an external clock for output modules or a signal for synchronizing multiple cards.

There are 3 dip switches for configuring the external clock/sync connector:

J1 - close for on board 50 ohm termination, open for high impedance
J2 - close for multi-board signaling (external sync), open for clock
J3 - close for DC coupled TTL clock, open for AC coupled 1Vpp sinusoid clock

where closed is towards the main board.

To synchronize acquisition/playback between multiple cards, J2 must be in place (closed) for both the master and slaves. The Master asserts the XSOE flags to drive the line. The J1 terminators should be open. Add J3 for 2.5V 10kohm pull-up/dn and diode protection on the input/output.

The PIC5s internal 8-bit test port can also be used to synchronize multiple cards. In this case the Master asserts TPOE to drive the test port and the slaves need the XTGO and XSTP flags.

The PIC5 onboard crystal is a fixed 100MHz clock. User crystals must be mounted on the I/O modules themselves. A programmable clock is available on the mainboard for digital signals.

NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC NeXtMidas macro.

PIC6 - PCI Express (8/4/2/1 Lane, Gen 1) PM x2

This card is a Gen 1 PCI Express card. If fits in either 8/16 Lane slots. Jumper J4 is closed for special PCIe training compatibility behavior.

The card has a status LED next to the edge connector SMB. When the card is booted, the green LED flashes at roughly 1Hz. The red LED indicates PC transfers to/from the card.

Mounting an I/O module requires approximately 0.6 inches of slot width. All external module connectors are available at the card's edge connector.

The edge connector has 1 SMB connector to provide an external clock for output modules or a signal for synchronizing multiple cards.

There are 4 dip switches for configuring the external clock/sync connector:

J1 - close for on board 50 ohm termination, open for high impedance
J2 - close for multi-board signaling (external sync), open for clock
J3 - close for DC coupled TTL clock, open for AC coupled 1Vpp sinusoid clock
J4 - close for PCI Express backwards compatibility mode

where closed is towards the main board.

To synchronize acquisition/playback between multiple cards, J2 must be in place (closed) for both the master and slaves. The Master asserts the XSOE flags to drive the line. The J1 terminators should be open. Add J3 for 2.5V 10kohm pull-up/dn and diode protection on the input/output.

The PIC6s internal 8-bit test port can also be used to synchronize multiple cards. In this case the Master asserts TPOE to drive the test port and the slaves need the XTGO and XSTP flags.

The PIC6 onboard crystal is a fixed 100MHz clock. User crystals must be mounted on the I/O modules themselves. A programmable clock is available on the mainboard for generating digital signals.

NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC NeXtMidas macro.

PIC7 - PCI Express (8/4/2/1 Lane, Gen 1/2) PM x2

This card is a Gen 2 PCI Express card. If fits in either 8/16 Lane slots. Jumper J4 is closed for special PCIe equalization.

The card has a status LED next to the edge connector SMB. When the card is booted, the green LED flashes at roughly 1Hz for Gen1 and 2Hz for Gen2. The red LED indicates PC transfers to/from the card.

Mounting an I/O module requires approximately 0.6 inches of slot width. All external module connectors are available at the card's edge connector.

The edge connector has 1 SMB connector to provide an external clock for output modules or a signal for synchronizing multiple cards.

There are 4 dip switches for configuring the external clock/sync connector:

J1 - close for on board 50 ohm termination, open for high impedance
J2 - close for multi-board signaling (external sync), open for clock
J3 - close for DC coupled TTL clock, open for AC coupled 1Vpp sinusoid clock
J4 - close for PCI Express equalization mode

where closed is towards the main board.

To synchronize acquisition/playback between multiple cards, J2 must be in place (closed) for both the master and slaves. The Master asserts the XSOE flags to drive the line. The J1 terminators should be open. Add J3 for 2.5V 10kohm pull-up/dn and diode protection on the input/output.

The PIC7s internal 8-bit test port can also be used to synchronize multiple cards. In this case the Master asserts TPOE to drive the test port and the slaves need the XTGO and XSTP flags.

The PIC7 onboard crystal is a fixed 100MHz clock. User crystals must be mounted on the I/O modules themselves. A programmable clock is available on the mainboard for generating digital signals.

NOTES:

  1. The headers on the board are static sensitive. Do not handle the board
    without taking proper static discharge precautions.
  2. Make sure all connectors are oriented properly.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC NeXtMidas macro.

SLIC3A - CardBus SlimPIC (32 bit, 33MHz, 3V) Tuners (GC4014 x1) A2D x2

INTRODUCTION

The ICE-SLIC3A is driven by an Analog Devices 21062 SHARC DSP and interfaced to the CARD-bus by an Altera FLEX10K30 programmable logic device. It contains two 100MHz 8-bit A2Ds, and one GC4014 Digital Tuner.

INSTALLATION

This card fits in a standard Type3 Card-bus slot. Slide it in ...

The center MCX plug is for triggering or an external clock. The left MCX plug (looking at top with card-edge facing down) is channel-A input 50ohm 1Vpp. The right MCX plug is channel-B.

NOTES: Be careful removing cables. Use a twisting motion while pulling.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC X-Midas macro. Special IOC programs are loaded to perform loopback tests for all components except the modules.

SLIC3D - CardBus SlimPIC (32 bit, 33MHz, 3V) Tuners (GC4014 x1) IOM x1

INTRODUCTION

The ICE-SLIC3D is driven by an Analog Devices 21062 SHARC DSP and interfaced to the CARD-bus by an Altera FLEX10K30 programmable logic device. It contains one 16-bit I/O Module site, and one GC4014 Digital Tuner.

INSTALLATION

This card fits in a standard Type3 Card-bus slot. Slide it in ...

The center MCX plug is for triggering or an external clock. The left MCX plug (looking at top with card-edge facing down) is channel-A input 50ohm 1Vpp. The right MCX plug is channel-B.

See the DRIVERS.HLP to install the software drivers.

MAINTENANCE

Hardware checkout procedures are automated in software by running the TEST procedures in the PIC X-Midas macro. Special IOC programs are loaded to perform loopback tests for all components except the modules.

Processor Modules

DTDM - Digital Tuner Demodulator Module

DTDMX - Digital Tuner Demodulator Module with larger FPGA

ZPPM - Virtex-5 based FPGA Module with DSP

V5M - Virtex-5 based FPGA Module

V6M - Virtex-6 based FPGA Module

I/O Modules

A2D - Analog to Digital Converter Module

This module converts analog signal voltages to 12-bit TTL at up to 65MHz. Signal lines are attached to the module by two coaxial cables, clock and data.

NOTE: The AD6620 has a minimum clock rate of 5MHz.

SERIES 2 CARDS:

The data is 1Vpp into 50 Ohms through a 1:4 RF transformer.

The clock is jumpered to be DC coupled TTL levels, an AC coupled 1Vpp sine wave, or a crystal installed on the module (optional). The clock also has a jumper that applies a 50 ohm termination to ground.

An internal clock from the mother board is also available via software control. It is the on-board crystal 40MHz divided by an integer from 1 to 65535.

Jumper Settings:

H3 - Closed for 50 ohm termination
H4 - Closed for DC coupled clock input (0-5V)
H5 - Closed for AC coupled clock input (1Vpp)
H6 - Closed for on-board oscillator clock input

The clock and data are brought out to the edge connector as follows:

Upper - A side data
UMid  - A side clock
LMid  - B side clock
Lower - B side data

SERIES 3 CARDS:


The data is 1Vpp into 50 Ohms through a 1:4 RF transformer. The clock is an AC coupled 1Vpp sine wave with 50ohm termination jumper.

Two clocks from the mother board are also available via software control. The internal clock (MUXCLK=I) is the on-board 40MHz crystal divided by an integer from 1 to 65535. A second socketed crystal (default=65MHz) is available as (MUXCLK=C).

Jumper Settings:

J1 - Closed to ground data connector sleeve
J2 - Closed to ground clock connector sleeve
J3 - Closed for 50 ohm termination of clock

The clock is the upper SMB and the data is the lower SMB per module. Note that the series 3 edge connector has its own SMB for the eXternal clock/sync signal. To use this clock apply the MUXCLK=X flag.

If both modules are A2Ds the SMBs will be ordered as:

Upper - A side data
UMid  - A side clock
Middle- External clock/sync
LMid  - B side data
Lower - B side clock

D2A - Digital to Analog Converter Module

This module converts 12-bit TTL data to analog signal voltages at up to 125MHz.

There are four clock sources, three located on the motherboard, and are selectable via software control. The default clock is an external source connected to the motherboard SMB connector, usually a 1Vpp sine wave. The internal clock (MUXCLK=I) is the on-board 40MHz crystal divided by an integer from 1 to 65535. The alternate clock (MUXCLK=C) is the socketed crystal X2 on the motherboard. The fourth source is a 125MHz crystal on the module. This is used to support high bandwidth test signals using a pattern programmed into the FPGA on the module. See PICFUNC for more details.

E2D - Differential ECL to Digital Converter Module

This module converts F100K Differential ECL signals to TTL. Signal lines are attached to the module by a 40 pin ribbon cable. It is best to remove the module from the card before connecting or disconnecting the 40-pin ribbon cable as this usually puts torque on the 24-pin module connector.

In standard configurations, the 40 pin connector will be cabled through the card edge connector to an 40 pin male IDC connector roughly 3-4 inches from outside of the chassis.

See HELP CARDS MIDASDSM for information on interfacing with a Midas switch.

D2E - Digital to Differential ECL Converter Module

This module converts TTL signals to F100K Differential ECL. Signal lines are attached to the module by a 40 pin ribbon cable. It is best to remove the module from the card before connecting or disconnecting the 40-pin ribbon cable as this usually puts torque on the 24-pin module connector.

SERIES 2 CARDS:

An external clock can be connected via SMB connector on the card edge and is jumpered to be DC coupled TTL levels or an AC coupled 1Vpp sine wave. The clock also has a jumper that applies a 50 ohm termination to ground.

An internal clock is also available via software control. It is the on-board crystal 40MHz divided by an integer from 1 to 65535.

H3 - Closed for 50 ohm termination
H4 - Closed for DC coupled clock input (0-5V)
Open   for AC coupled clock input (1Vpp)

In standard configurations, the 40 pin connector will be cabled through the card edge connector to an 40 pin male IDC connector roughly 3-4 inches from outside of the chassis.

SERIES 3 CARDS:

There are three clock sources, all located on the motherboard, and are selectable via software control. The default clock is an external source connected to the motherboard SMB connector, usually a 1Vpp sine wave. The internal clock (MUXCLK=I) is the on-board 40MHz crystal divided by an integer from 1 to 65535. The alternate clock (MUXCLK=C) is the socketed crystal X2 on the motherboard.

See HELP CARDS MIDASDSM for information on interfacing with a Midas switch.

PE2D - Positive Differential ECL to Digital Converter Module

This module converts F100K Differential ECL signals to TTL. Signal lines are attached to the module by a 40 pin ribbon cable. It is best to remove the module from the card before connecting or disconnecting the 40-pin ribbon cable as this usually puts torque on the 24-pin module connector.

In standard configurations, the 40 pin connector will be cabled through the card edge connector to an 40 pin male IDC connector roughly 3-4 inches from outside of the chassis.

T2D - Differential TTL to Digital Converter Module

This module converts Differential TTL signals to TTL. Signal lines are attached to the module by a 40 pin ribbon cable. It is best to remove the module from the card before connecting or disconnecting the 40-pin ribbon cable as this usually puts torque on the 24-pin module connector.

In standard configurations, the 40 pin connector will be cabled through the card edge connector to an 40 pin male IDC connector roughly 3-4 inches from outside of the chassis.

See HELP CARDS MIDASDSM for information on interfacing with a Midas switch.

D2T - Digital to Differential TTL Converter Module

This module converts TTL signals to Differential TTL. Signal lines are attached to the module by a 40 pin ribbon cable. It is best to remove the module from the card before connecting or disconnecting the 40-pin ribbon cable as this usually puts torque on the 24-pin module connector.

In standard configurations, the 40 pin connector will be cabled through the card edge connector to an 40 pin male IDC connector roughly 3-4 inches from outside of the chassis.

See HELP CARDS MIDASDSM for information on interfacing with a Midas switch.

LV2D - LowVoltageDifferentialSignaling to Digital Converter Module

This module converts LVDS signals to TTL. Signal lines are attached to the module by a 40 pin ribbon cable. It is best to remove the module from the card before connecting or disconnecting the 40-pin ribbon cable as this usually puts torque on the 24-pin module connector.

In standard configurations, the 40 pin connector will be cabled through the card edge connector to an 40 pin male IDC connector roughly 3-4 inches from outside of the chassis.

See HELP CARDS MIDASDSM for information on interfacing with a Midas switch.

D2LV - Digital to LowVoltageDifferentialSignaling Converter Module

This module converts TTL signals to LVDS. Signal lines are attached to the module by a 40 pin ribbon cable. It is best to remove the module from the card before connecting or disconnecting the 40-pin ribbon cable as this usually puts torque on the 24-pin module connector.

In standard configurations, the 40 pin connector will be cabled through the card edge connector to an 40 pin male IDC connector roughly 3-4 inches from outside of the chassis.

See HELP CARDS MIDASDSM for information on interfacing with a Midas switch.

GXD - GigaBit Ethernet Interface Module

This module converts IEEE Gigabit signals to 16 bit data and back. The Ethernet protocol is optional. The FPGA on the module implements the protocol to offload the rest of the card for processing.

UDP - GigaBit Ethernet / Protocol Interface Module

This module converts IEEE Gigabit signals to 16 bit data and back. The Ethernet/UDP/SDDS packets are optional. The FPGA/MAC chip on the module implements the protocol to offload the rest of the card for processing. The IOM=xxx parameter controls the packet handling modes of the card as follows:

IOM=UDPXD	- UDP input module
IOM=DXUDP	- UDP output module
IOM=SDDSXD	- SDDS input module (use UOPT flag for raw packet)
IOM=DXSDDS	- SDDS output module

In SDDS configurations, the SDDS header is normally stripped off. Data is expanded to 16 bits internally and can be read as 1, 8, or 16 bits regardless of the SDDS packet format. The 16 bit form is presented to the tuners, and SDDS timecode is handled by the ICE libraries using the TC=SDDS flag.

SONET - Synchronous Optical Network Interface Module

This module converts Sonet Data to 16 bit data and back. The Sonet Rev 1 Modules operate at OC3 or OC12 rates.The Sonet Rev2 modules operate on Port B side at OC3/OC12/OC24 or OC48 rates with port A operating at OC3/O12 rates only. The IOM=xxx parameter controls the data handling of the module:

IOM=SNTXD	- Sonet Rev 1 input  module
IOM=DXSNT	- Sonet Rev 1 output module
IOM=SNTR2XD	- Sonet Rev 2 input  module
IOM=DXSNTR2	- Sonet Rev 2 output module

Sonet Line descrambling is performed on the modules such that data comes into the system in a user "readable" format. Modules are also capable of realtime demux of lower rate signals from high band width signals, i.e. OC3 from an OC48. Check with www.rumel-online.com/software.htm for a list of software switches and examples for how to enables modes on each of these modules.

CXD - Communications Protocol to Digital Converter Module

This module converts HDB3 E3/E2/E1 to digital clock and data, and/or converts digital clock and data to HDB3 E3/E2/E1.

The <rate> parameter must one of:

E1: 2048000 Hz
E2: 8448000 Hz
E3: 34368000 Hz
T1: 1544000 Hz (requires crystal option)
T?: 32768000 Hz (requires crystal option)

The <gain> parameter can introduce 0, -3, -6, or -9 dB of attenuation.

This upper SMB is input, the lower SMB is output.

UXD - User to/from Digital Converter Module

This module is a bread board with 5V power/ground and interface connectors for a user designed I/O Module. The layout supports up to 4 SMBs, a 16 strand ribbon, or other. See associated ICEUXD.GIF file for layout specifics.

This module can be assembled to input or output TTL, RS422, or other user specified electrical interfaces.

FPDP - Front Panel DataPort I/O Module

FPQC - Front Panel DataPort / QC64 I/O Module

NFXD - NGC Fiber Input/Output I/O Module

CDR2D - Clock Data Recovery Input I/O Module

DR2D - Differential Receiver I/O Module